Additional FeaturesHigh Performance RISC CPU:C Compiler Optimized Architecture:Optional extended instruction set designed to optimize re-entrant codeUp to 1024 bytes Data EEPROMUp to 64 Kbytes Linear program memory addressingUp to 3936 bytes Linear data memory addressingUp to 16 MIPS operation16-bit wide instructions, 8-bit wide data pathPriority levels for interrupts31-level,..