Additional FeaturesHigh Performance RISC CPU:C Compiler optimized architecture/instruction setData EEPROM to 1024 bytesLinear program memory addressing to 64 KbytesLinear data memory addressing to 4 KbytesUp to 16 MIPS operation16-bit wide instructions, 8-bit wide data pathPriority levels for interrupts31-level, software accessible hardware stack8 x 8 Single-Cycle Hardware Mul..